This is because of a glitch in measuring of BCLK clock, I'm sure your PCIe bus clock is OK.
You might try to disable the "Use HPET" option in HWiNFO to see if that fixes it, or disable "Periodic polling".
Hardware-bus frequency is determined by the generator covered loop PLL (phase locked loop) consisting of reference (usually stabilized quartz) generator, a phase comparator and the divider (multi-stage counter) output signal which controls the common voltage-controlled oscillator (VCO) with which, and removed a clock for the bus . In some implementations, the PLL divider is used with a fixed division factor, in other counter division factor (since it is always an integer selected level defined counter status which should coincide by "AND" RESET for generating counter output signal is used as the signal) can be controlled, and then to reduce energy consumption and heating circuit clock frequency while reducing the processing load is reduced, the scheme does not lead to a breach of health in general. The main condition is the output frequency of the bus outside the acceptable standard values, and if the frequency values are within the range, then everything is in order.