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I thought polling is done on all cores at once using one thread per core. If it's done in series then I obviously misinterpreted that part. An issue of CPU counters just because of disabling all C states (except C6) and E cores seems rather unlikely, does it not?! I will check this again and...

That and the P-core clocks reading as 55/60/60/60/60/59/59/59 while turbo max restrict them to 60/60/59/58/57/56/55/55. At no time does the CPU concurrently clock 4 cores to 60x + 3 cores to 59x, so the HWinfo readings are way off. I assume that these are the last values before entering C6...

HWinfo gets super confused by my current test setup: all cores max 60x, turbo max 60x for 2 (!) concurrent cores (60/60/59/58/57/56/55/55), all C states except C6 disabled (including C1E), all E cores disabled.

Thanks for the explanation. Turns out that "Turbo Ratio Limits - AVX2" is kind of correct. The CPU does hardlock AVX load to 58x max regardless of the AVX offset, but it still allows other cores to run non AVX load at 59x while AVX load is present on single cores.

Works great, thank you! Maximum Per-core Ratio Limits (Fused): 55, 55, 58, 58, 55, 55, 55, 55, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43 Maximum Per-core Ratio Limits (Current): 57, 56, 59, 59...

Wow, very nice. Thanks a lot and happy holidays! :)

Likely also useful, but since these never change it's only a one-time information. Overrides change a lot while working on a stable per core OC, so being able to read their current values would be useful. These override ratios also dictate Windows scheduler's priorities (it always prioritizes...

Great, thank you! :-) Unfortunately the values are not correct for my setup, though. HWinfo: 55, 55, 58, 58, 55, 55, 55, 55, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43 BIOS: 56, 58, 57, 55, 55, 55, 59, 59 43, 43, 43, 43, 43, 43, 43, 43, 45, 45, 45, 45, 44, 44, 44, 44

Unfortunately I do not know what "Core Performance Order" is, something like AMD's CPPC maybe? What I mean, though, is that CPUs do not have to use the same maximum frequency on each of their cores. By default my 13900K uses a maximum of 58x on a P cores, but via BIOS settings I changed that to...

Hello. Currently HWinfo only reports the "CPU Turbo Max" for the fastest core and then the "Turbo Ratio Limits" per concurrent cores. But unfortunately it nowhere seems to list per core Turbo Max values? My current per core Turbo Max values would be: 59/59/56/56/56/55/58/58 Furthermore the...

Thanks for the extra information. Increasing the polling rate to reduce noise on Effective Clocks seems like the best bet then. Unfortunately Effective Clocks still gets dominated by C states, which is a problem when a single thread of load is shifted between 2 HT cores of the same physical core...

Would disabling the Core Clocks (+Ring?) and Ratio sensors disable that extra polling load and thus increase accuracy of the Effective Clocks sensors (due to less Hwinfo load)?

I already disabled monitoring in OCCT, but it didn't help. Since this does not seem to happen with fixed affinity load of P95 I will report it to the OCCT author.

Increasing HWInfo's priority does not help, neither High nor Realtime. And OCCT's own load threads already only use priority 1 (base and dynamic) anyway. So there seems to be more afoot here than just scheduler time slots!?

1. Ah, yes. This makes sense and is one reason why I try to find a good balance between poll rates being too high (additional load) or too low (not enough information). But having the poll action itself cause clock changes wasn't on my list entirely. Does this "active polling" also happen for...

I tried the current Beta and noticed something I was not aware of before. This is independent of sensor latencies (only 0 ms sensors active): When I create constant load with fixed CPU core affinity, like 3 hyperthreaded cores of load in OCCT (6 threads) then HWinfo's polling rate drops...

Thanks for the quick answers. 1. So essentially it is "bad luck" when the Core Clocks multiplier maximum is not recorded at the time of the polling period. I could increase the polling rate then, but at the cost of creating more background load via HWinfo. I wish the Effective Clocks could be...

Hello. There are three oddities about "Core Clocks" that make me wonder about accuracy and even reliability of the measurements. The following screenshots are on a 13900K. I may be understanding these wrong, though?! 1. Core Clocks may not catch maxima that Effective Clocks do catch. True...

Very nice. Of course we don't expect absolute millisecond precision. The biggest confusion currently happens when HWinfo polls notably slower than what is set up, because of sensor latencies that users (including me in the beginning) usually know nothing about. So from my point of view this is a...

Great. Thanks for looking into this. :)