Search results

HWiNFO reacts stronger to C-states than RM (which hardly reacts at all). In the following screenshot and animated GIF (attachment) both are set to 1 second polling interval. C0 Residency, Core 0 Effective Clock, RM Core 0 That being said, I even prefer that, but only if HI counts times of...

Is it expected that HWiNFO displays different effective clocks than RyzenMaster when cores are not 100% in C0 state? RM does not offer averages over time, so it's not easy to compare, but the current readings are different. Sometimes RM is higher, sometimes lower, but for a specific load it...

Thanks Martin. I am currently trying to create a "Clock Stretching" sensor that calculates C-states out of effective clocks, but polling latency and rounding errors seem to be a problem. @Zach Yes, it's common, but one would expect the "better" CCD to be more power efficient, instead of the...

Here are my custom "sensors" summing up the already existing "Core X Power" sensors. This more easily demonstrates how CCD0 consumes more power under the equally distributed load (P95) compared to CCD1. Since CCD0's effective clock is lower while consuming more power I will add average...

The main reason why I am currently preferring clock stretching as an explanation for non C-state induced frequency limiting is that C1 likely is still slower and more costly than clock stretching. And even changing the multiplier could be slightly more costly, which may be the reason why AMD...

Over at the Overclock.net forum, someone posted a link to the "Adaptive Clocking in AMD's Steamroller" article describing how AMD's clock-stretching works. So based on even the small cost of C1 (latency + enter/exit power cost), the explanation of AMD's clock-stretching and our discussion here...

But no effective minimums are measured at all by the multiplier sensors at all. At 50 ms polling rate and long enough measuring we should expect at least some multiplier drops to be measured even if those are done within 1-20 ms. This seems to suggest that either the multiplier register (?)...

Difference varies by load profile, but in the screenshot on page 1 it is about 0.25 MHz on CCD0. https://www.hwinfo.com/forum/threads/core-effective-clocks-at-100-c0-state.7325/post-30863

This is understood. The question is how is the clock lowered when all C-states are disabled? If it is by multiplier, should we not be able to catch that with a high enough polling rate and long enough measurement time?

So at 100% C0 state the effective clock is lowered by the core being turned off in between, akin to low C-states (C1-C3 non deep)? Wouldn't that cause on/off current spikes? Does this reduce voltages or just stop the clock? Thanks for pointing to custom sensors, that looks useful. :)

So let me simplify my main question: Are the effective clocks reduced by means of the multiplier changing quickly or by other means (with C-states disabled)? If it is the multiplier, shouldn't we be able to catch that unless the multiplier register does not report it?

Sorry, I found the perf sensors collapsed under "Core Clocks". I did not expect them to be there and usually don't care for clocks but prefer to watch multipliers instead. What I meant with the per-CCD power was a simple sum of the per-core powers in blocks of CCDs. It's likely not worth the...

Nope, I don't have these, but CTR lists CPPC order and I already confirmed that Windows thread scheduler makes use of the correct order (both with and without core parking). I also mentioned earlier that Prime95 fixes affinities of its threads to specific cores (likely for cache coherency) and...

Could it be that the rather low power "CPU SoC" is *not* the IO die but everything outside of CCDs and IO die? Thus the 20 watts power could be contributed to the IO die and might even increase with PCIe and USB load?! 20(+) watts would also fit the chipset (southbridge) needing active cooling...

I noticed that on Zach's 3600 Package/PTT only measures as 10 watts over Core + SoC. Is that to be expected with the 3600 using the same IO chip as the 5900X?

I will do that tomorrow, but I can already tell you that there are no C1 or C6 residencies at any time, because I specifically turned off C-states for these tests. It is 100% C0 state. And my screenshot already shows core usage to be 100%. "Perf # x/x" is not available here (also not just hidden).

About the different binned CCDs: This is to be expected, with CCD0 being the "better" one and CCD1 being the "worse" one. According to CPPC the best core of CCD1 is worse than the worst core of CCD0. What is surprising, though, is that CCD0 is the one that is limited further down in effective...

Snapshot CPU polling makes no difference. Using different polling intervals makes no difference. If the CPU changes multipliers between 1 and 20 ms then I still would expect to catch at least one such decreased multiplier at a polling rate of 50 ms (or longer polls), even more so if...

To underline, the drop from 20 watts to 14 watts is induced by C-states, not by the CPU having no load to process. I find this rather strange, since I would expect all C-state related power readings to fall under the Core or SoC moniker?!

What I mean is: Even at 50 ms polling the minimum Multiplier reading never hits as low as the Effective Clock reading. That is even with constant 100% load, C-states disabled and effective clock constantly decreased due to hitting one of the PBO limits. At such high polling rate and such...