The clock frequency for DDR, DDR2, DDR3, DDR4, DDR5 memory multiple of its effective frequency due to the fact that the data is transmitted in packets of a few lines per cycle, with the operation itself occurs twice - and the clock "01" (rising or rising edge) at the change, and the it changes "10" (falling or trailing edge), and furthermore by means of special circuits allow the use of these devices for simultaneous data transfer in both directions - to and from the device chip and a chip of the device. This mode is called duplex signalers.
The only fundamental difference between DDR3, DDR4, DDR5 from DDR and DDR2 is only the value of the package. The DDR is one line in two DDR2 and DDR3 is used since the size of the package in four lines. Therefore, the actual clock speed of memory chips DDRh equal to their effective frequency divided by the size of the package. But the use of packet transmission in the DDR2 and ascending above leads its delay as the time interval between the arrival of the control signal to the chip and the moment the operation is completed defined as the steady state of the circuit or the time of data availability. Circuits internal delay depends on their physical and electrical circuit elements and active parameters are typically about 60 - 80 ns per cell. If the duration of the control signal is less than the intrinsic delay her cell steady state will be unpredictable - there memory failure. And it is this like effects depends on the quantum phenomena in semiconductor and limits the increase in clock frequency ( "overclocing"). Microchips have some inventories on the aging of the crystal, the deflection voltage power supply and the spread of technological dimensions of structures defining the frequency properties of the circuit, but it is not large, typically on the order of a few percent and the plant with an output test performs their rejection for maximum working frequency than that is not recommended, especially taking into account the development of the mortgaged their lifetime chip - usually about 8 - 10 years, after which allow them to fail suddenly.