HWiNFO v6.21-4040 Beta released

Martin

HWiNFO Author
Staff member
HWiNFO v6.21-4040 Beta available.

Changes:
  • Updated reporting of PPT/TDC/EDC limits when OC-Mode active (no limits).
  • Added monitoring of Effective CPU Core VID on AMD Zen CPUs.
  • Multiple sensor items can now be configured at once via settings.
  • Added support of selective sensor items for logging.
  • Improved FCLK monitoring on AMD Zen2.
 
On C7HWIFI using UEFI 0002 (AGESA 1.0.04.B) FCLK is not reducing on no CPU load, does on v6.20-4030. Is it the ASUS UEFI or HWINFO issue? TIA :)
 
Well the situation is following:
- v6.20 used a FCLK counter that (unlike the value in RM) did reflect DF C-States, but it was observed that after some time this counter could go crazy and started to report invalid values (above limit)
- So in v6.21 Beta I switched to a different method of reporting FCLK (set point). The value shown now should match RM, but doesn't reflect all power management states. It should be more-less stable.
 
Hey Brother Martin. I hope you and your family had a great Christmas and I hope you all have a Happy New Year as well. Thanks for your continued support with HWiNFO. Much appreciated.

Question: What does the new (perf #--) text for each CPU core mean?

HWiNFO is one of the main attractions in my latest YouTube video.

 
Thank you and Merry Christmas to you too!
The 'perf#" values denote the Core Performance Order index. I added this information into sensors as I think it might be useful for checking core utilization/clock with respect to the favored cores order.
If there are 2 numbers shown (perf# 1/2), then:
- The first number specifies the CPPC order as defined by the firmware via to Windows. This is available on AMD Zen2 CPUs with latest firmware and Windows 10 and it's the order that's used by Windows scheduler.
- The second number specifies the favored core order defined by hardware
Note that the CPPC order usually doesn't match the hardware one. Reasons for this have been explained by AMD as there are other criteria involved to define the OS-aware performance order for optimal power/performance.
 
Thanks for info Martin, hope you and your family had a good Christmas and wish all the best for the New Year.

Currently using the v6.20-4030 as like seeing the FCLK reflect DF C-States. Out of the 3x R9 3900X I had been testing, one at stock shows excessive FCLK then set value.

Do you think in future with say improved AGESA the other method of FCLK counter will become default again? if not is there a edit to ini I can make to use the other counter on a later HWINFO version?

@Mr. Fox this post by The Stilt has some further info on CPO.
 
Thanks Gup, and all the best to you and your family too!
I really don't know if AMD will fix the current FCLK counter, but if this would happen, I will surely switch back to that one. But currently I think it's better to report the rather static set-point than the actual DF C-State aware counter which sometimes goes crazy and would confuse most users.
 
Thank you and Merry Christmas to you too!
The 'perf#" values denote the Core Performance Order index. I added this information into sensors as I think it might be useful for checking core utilization/clock with respect to the favored cores order.
If there are 2 numbers shown (perf# 1/2), then:
- The first number specifies the CPPC order as defined by the firmware via to Windows. This is available on AMD Zen2 CPUs with latest firmware and Windows 10 and it's the order that's used by Windows scheduler.
- The second number specifies the favored core order defined by hardware
Note that the CPPC order usually doesn't match the hardware one. Reasons for this have been explained by AMD as there are other criteria involved to define the OS-aware performance order for optimal power/performance.
Thank you for explaining that for me. :)

Thanks for info Martin, hope you and your family had a good Christmas and wish all the best for the New Year.

Currently using the v6.20-4030 as like seeing the FCLK reflect DF C-States. Out of the 3x R9 3900X I had been testing, one at stock shows excessive FCLK then set value.

Do you think in future with say improved AGESA the other method of FCLK counter will become default again? if not is there a edit to ini I can make to use the other counter on a later HWINFO version?

@Mr. Fox this post by The Stilt has some further info on CPO.
Thank you, too. :cool:
 
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