HWiNFO v6.21-4055 Beta released


HWiNFO Author
Staff member
HWiNFO v6.21-4055 Beta available.

  • Updated reporting of PPT/TDC/EDC limits when OC-Mode active (no limits).
  • Added monitoring of Effective CPU Core VID on AMD Zen CPUs.
  • Multiple sensor items can now be configured at once via settings.
  • Added support of selective sensor items for logging.
  • Improved FCLK monitoring on AMD Zen2.
  • Enhanced sensor monitoring on ASRock X570 Creator and X570 AQUA.
  • Updated USB ID database.
  • Improved reporting of advanced parameters on AMD Zen2-based CPUs/APUs.
  • Added monitoring of advanced parameters on AMD Zen1-based CPUs/APUs.
  • Added monitoring of C-State residency on AMD Zen CPUs/APUs.
  • Fixed reporting of DIMM SPD information on Supermicro H11SS series.
  • Added AMD Radeon RX 5600 XT.
  • Added support of Aquacomputer Octo.
  • Added ability to use simple formulas (including other sensor values) for custom sensors. See here for more details.
  • Added support of Corsair H115i RGB PRO XT.
Last edited:
"Added support of Corsair H115i RGB PRO XT"

Still shouldnt be used with Corsair software like iCUE and LINK?
I have the H110i 280mm (with iCUE) and disabled in HWiNFO... should I leave it this way?
Yes, Corsair software still doesn't play fair with others AFAIK, so it's strongly recommended not to run it with any other monitoring tool.
  • Added monitoring of Effective CPU Core VID on AMD Zen CPUs.
Any explanation on this please?
I know that "Core x VID" is what each core is asking, "CPU Core Voltage (SVI2 TFN)" is what actually the CPU is getting, but "CPU Core VID (effective)"?
Always is higher from SVI2 TFN by a small margin.
Despite seeing different voltage values requested by particular cores (VID), in reality only a single voltage is supplied to the CPU. This is the voltage level that "wins" among all requests and this is the Effective CPU Core VID.
Aa ok...
And the relation with SVI2 TFN core voltage?
It looks like almost always the VID effective is slightly higher than SVI2 TFN. About 0~20mV (current value), 5~15mV (average value).
Min/Max are the same.
SVI2 TFN core voltage is the voltage really provided to the CPU by the VRM.
“CPU Core VID effective” is the (eventually) requested(?), the one that wins among VIDs, and SVI2 TFN is what actually gets.

What confuses me is that individual VIDs are much lower than any of the other 2 and the effective is even a little higher than SVI2 TFN.
Vdroop is most probably the reason for difference between voltage requested and supplied.
But I'm not sure about the difference between individual VIDs and the effective one, most probably the SMU applies some additional offset to guarantee sufficient stability.
This is what looks like in every case scenario

2 different of light loads:



During Cinebench R20:


FarCryNewDawn gameplay: