incorrect jedec timings table

[pha]

For example DDR4-2133P can operate at 1067 MHz with CL15 and CL16.
And there is no 1000Mhz frequency
[attachment=3471]
(HWInfo v6.06.3770)


Here is JEDEC JESD79-4 specs for 2133 memory
[attachment=3473]

Correct values for my module is
[attachment=3472]
(Thanks Thaiphoon Burner)

 

[Martin]

OK, I will adjust this. But I'm not sure if all modules fully adhere to speed bins defined by JEDEC.

 

[pha]

In new version 3820 timings are looking better.
But not enough

[attachment=3479]
XMP profile have only one preset of timings and voltage.
My memory modules have only "16-18-18-36 3200Mhz 1.35v".

PS:there is memory with 2 profiles = 2 presets...

 

[Martin]

But XMP defines also a set of CAS Latencies supported, so the values shown above should be correct as long as they fall within that set (which they do).
I will adjust rounding of some clocks in the report and remove some duplicates..