PCI BUS Hierarchy

[h4rp00n33r]

Hello folks!
I'm struggeling with the representation of the PCI BUS hierarchy in HWiNFO64. Here's an example:

• PCIe Bus #2 works with PCIe 3.0x8.
• PCIe Bus #3 is connected to PCIe Bus #2 and works with PCIe 3.0x8. So far, so good.
• PCIe Bus #8 works with PCIe4.0x16. But how can this work when it is connected to PCIe Bus #3 which runs only PCIe 3.0x8? Following the hierachy of the diagram, PCIe Bus #2 and PCIe Bus #3 are bottle necks regarding the bandwidth, aren't they?

Thanks for your help in advance!

 

[Martin]

PCIe Bus #8 is most likely a virtual/internal bus, you should be able to determine this if you examine details of particular bridges in the path. Check the Maximum and Current Link width parameters.

 

[h4rp00n33r]

Okay thanks for your quick reply.

Here are the details of the bridge the PCIe Bus #2 is connected to:


And here are the details of the bridge the PCIe Bus #8 is connected to:


So is Bus #8 limited by Bus #2/Bus#3?

 

[Martin]

Yes, it's not a true x16 link. The entire chipset is connected using a x8 link and some of the downstream links (i.e. SATA) are multiplexed

 

[h4rp00n33r]

Okay, thanks a lot.