Zen 3 Package Power

Timur Born

Well-Known Member

I wonder why on Zen 3 (5900X) the CPU Package Power (and CPU PPT) is always 20 watts over Core + SoC in all load states? And why is there no sensor corresponding to these 20 watts of power consumption?

CPU Package Power also reads higher than both PIN and POUT, which I assume speak to the lacking quality of corresponding VRM sensors (they only report in broad steps)?
CPU Package Power and PPT account for additional rails that can't be measured, but are estimated.
Thanks for the quick reply! If the estimation is higher than what the VRM's PIN or POUT measure, does that not point to the estimation being too high (even if POUT cannot fully be trusted anyway)?
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Please read again my post above, you seem to be missing the point. VRM's POUT (or SVI2 TFN) reports only those rails that can be measured.
Ah, I thought you only meant CPU Core and SoC can be measured (from the CPU side of things). Indeed I did not understand that VRM PIN/POUT are missing rails, thanks for the clarification.

What immeasurable parts of the CPU package are estimated to permanently consume 20 watts then?
With the memory controller being part of the cIOD I thought that VDDIO_MEM based power consumption would be part of SoC power?

VDD18 might be worth revisiting, because it measured as 1.844 V when set to Auto/1.8 V.

Not sure what RoC is? I tried to search for it, but only came up with Radeon Open Compute platform?!
SoC power covers the VDDCR_SOC rail only, VDDIO_MEM is a separate rail.
ROC = Rest-of-Chip - a pre-calculated sum of all minor rails.
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Ah, Rest-of-Chip is listed as a dedicated sensor on my 9900K and measures in the low single digit watts range.

I lowered VDD18 to 1.76 V in AGESA to have it measures as 1.80x V now. But it makes no difference to power consumption, neither in HWiNFO nor at the wall.

I did notice, though, that the delta between Package/PPT and Core+SoC decreases to about 14 watts when C-states are engaged. This is independent of actual CPU load, because the same idle load without C-states keeps the delta at 20 watts. So one part of those 20 watts is lowered by 6 watts when cores (and SoC?) are HALTed. I did not check if C1 is enough for that or if C6 is needed, though.
To underline, the drop from 20 watts to 14 watts is induced by C-states, not by the CPU having no load to process. I find this rather strange, since I would expect all C-state related power readings to fall under the Core or SoC moniker?!
I noticed that on Zach's 3600 Package/PTT only measures as 10 watts over Core + SoC. Is that to be expected with the 3600 using the same IO chip as the 5900X?
Could it be that the rather low power "CPU SoC" is *not* the IO die but everything outside of CCDs and IO die? Thus the 20 watts power could be contributed to the IO die and might even increase with PCIe and USB load?! 20(+) watts would also fit the chipset (southbridge) needing active cooling with it effectively being the same die.
I have seen differences in CPU SoC power consumption over same CPU line, or even same SKUs. From 6~7W to 25~26W. It must depend on the system configuration and maybe on board's AGESA implementation (Vendor's BIOS).
Many factors contribute to SoC consumption.
CCD count, SoC voltage, UMC (UCLK) voltage, IF (FCLK) voltage, frequencies, DRAM density (sticks/ranks), system load, power plan (=CPU reaction time, 1~20ms) and perhaps also the direct links to CPU (PCI-E, USB etc).
Its not an easy task to determine the exact specifications.

For instance, you've seen on mine the SoC power between 11 and 14W. If I undo the DRAM OC to default (DRAM frequency/voltage, SoC voltage, UMC/IF voltage) SoC power will drop under 10W.
Sorry to bump old thread, but I was curious about the same thing as OP and found this:

The guy explains it in great detail.
He also created a tool to show more details about Zen3 power consumption.

Maybe it can be incorporated to HWiNFO as well?
Problem here is that not all voltage/power delivery rails have a capability to measure their current/power consumed.
We can only report power consumption of really measured rails or some minor ones that can be reliably estimated based on certain activity criteria.