hwinfo64 5.11-2730 have question,about voltage.
- Thread starter Enk
- Start date
VictorVG
Well-Known Member
The appearance of such figures can be explained by the peculiarities of CMOS circuitry chips - their input stages have a very high input impedance (10E9 - 10E12 Ohms) and small input capacitance of the gate - usually within a few pF which can cause damage by static electricity. To prevent the breakdown of the circuit transistor gate often shunt voltage divider, which at the same time shifts the operating point of the FET in the linear region of its current-voltage characteristics (CVC) and probably the chip measures the offset voltage presence on this input, and judging by its value this input circuit is not connected to ground the device. This is acceptable, but it is incorrect because the circuit solutions can lead to errors in the measuring circuit.
Exactly what measures the chip on the data input I could tell you after the analysis of the concept device, but no manufacturer will provide it for that outsider engineer, moreover, even if he will give a document called "The electrical circuit of the device ..." in he often made mistakes that make schematics collected on it the device inoperative - a real schematic diagram of a commercial secret of the manufacturer.
Exactly what measures the chip on the data input I could tell you after the analysis of the concept device, but no manufacturer will provide it for that outsider engineer, moreover, even if he will give a document called "The electrical circuit of the device ..." in he often made mistakes that make schematics collected on it the device inoperative - a real schematic diagram of a commercial secret of the manufacturer.
