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I meant clock (multiplier) capturing in C0 state. All my tests were done with C-states disabled.

Here is another source of confusion that is easy to misunderstand: This seems to suggest that core multiplier measurements fail to provide correct numbers due to polling restrictions. But even at 50 ms (20x per second) and *constant* CPU limitations the minimum multiplier numbers don't catch a...

Ah, Rest-of-Chip is listed as a dedicated sensor on my 9900K and measures in the low single digit watts range. I lowered VDD18 to 1.76 V in AGESA to have it measures as 1.80x V now. But it makes no difference to power consumption, neither in HWiNFO nor at the wall. I did notice, though, that...

Slap me, I am stupid. Unknowingly I still had custom per core CO values set in AGESA from an older test-run. So this explains the different CCD frequencies under P95 load. If HWiNFO really relies on a hardware register then I have to find out what is the limiting factor. I fear it will be EDC...

With the memory controller being part of the cIOD I thought that VDDIO_MEM based power consumption would be part of SoC power? VDD18 might be worth revisiting, because it measured as 1.844 V when set to Auto/1.8 V. Not sure what RoC is? I tried to search for it, but only came up with Radeon...

Thanks for the link and reminder that RyzenMaster can be used to verify the results. Unfortunately the linked explanation and following discussion kept emphasizing halted C-states, which I specifically disabled to better understand effective clock. Only after several read-overs did I understand...

Ah, I thought you only meant CPU Core and SoC can be measured (from the CPU side of things). Indeed I did not understand that VRM PIN/POUT are missing rails, thanks for the clarification. What immeasurable parts of the CPU package are estimated to permanently consume 20 watts then?

Hello. I wonder on what basis does HWiNFO calculate "Core Effective Clocks" to be lower than core multiplier based clocks when the CPU is 100% in C0 state? And why are "Core Effective Clocks" listed as considerably lower (300 MHz) for CCX0 on my 5900X when CCX1 is considered the worse CCX with...

Thanks for the quick reply! If the estimation is higher than what the VRM's PIN or POUT measure, does that not point to the estimation being too high (even if POUT cannot fully be trusted anyway)?

Hello. I wonder why on Zen 3 (5900X) the CPU Package Power (and CPU PPT) is always 20 watts over Core + SoC in all load states? And why is there no sensor corresponding to these 20 watts of power consumption? CPU Package Power also reads higher than both PIN and POUT, which I assume speak to...

I like the tooltip function, but I often turn it off, because it keeps refreshing with every single pixel movement of the mouse. This causes unnecessary CPU load which then gets measured by HWiNFO. Please consider implementing a delay time for the tooltip.

Good call, there were two sensor categories listed as up to 90 ms. So I hid every sensor (category) that takes longer than 5 ms, that only left 2 categories at 4-5 ms (all sensors below that 0 ms) and one category at 1 ms, everything else is 0 ms. Still at 100 ms polling rate HwInfo only seems...

I experience a similar issue using an AMD 5900X + W10 20H2 + HwInfo 7.03, but this time changing Windows timer resolution does not seem to have an impact.

And thanks for this change indeed, it is well appreciated! :) You are correct, disabling Write Direct solves this little problem and it is not significant. Just reporting FYI.

Ahoi. Thanks for the latest version (6.40). Small issue: when poll rate is under 200 ms and Debug mode is enabled then HWinfo struggles to draw its own GUI in the settings window. When I switch tabs it only managed to draw a single line and leaves the rest of the window blank. Regards!

I will keep an eye on that then and report back.

9900K, 8 cores / 16 threads. I appended a compressed (7Z) archive including both the report and debug files in the first post. That should answer all questions about my hardware setup. ;) Debug mode behavior reflects behavior when the Windows timer resolution is increased to 0.5 - 1 ms. But...

Thanks for the explanation about sensor polling when the heading is still enabled. I suspected that, but wasn't sure. That being said, for the polling timer test I did disable the headings already and the accumulated Profiling Time of all remaining sensors was less than 10 ms (more like <5 ms)...

Hello, on my W10 installation HWinfo's sensor polls/displays at slower rates than what is set up as Global polling rate. I reported this problem sometime last year and it is still present in the latest 6.34-4300. - When the Windows system timer is kept to its default of 15.625 ms and all...

Thanks Martin. You are right about the switching frequency, but I still expected *all* core multipliers to be lowered at once during mixed load when AVX load hits any single core, as demonstrated to happen in my constant AVX load test. I did not consider that HWinfo likely reads those...