But no effective minimums are measured at all by the multiplier sensors at all. At 50 ms polling rate and long enough measuring we should expect at least some multiplier drops to be measured even if those are done within 1-20 ms.It should be by multiplier, but I wouldn't take the discrete clock values into account as those might not catch the right peak.
This pertains to system with broad input frequency ranges, though, while our CPUs only have to deal with one input frequency (100 MHz).In practice, latency (delay) can be incurred at each frequency transition as frequency-multiplier circuitry stabilizes the system clock at its new frequency following each frequency change.
So unfortunately still not entirely clear for those of us who don't know how frequency multiplying is implemented in modern CPUs.Conversely, injection-locked oscillators exhibit fast lock times, but tend to have a narrow input frequency range and thus limited frequency agility.
This seems to be a per CCD correlation, though, not a per Core one (my "worst" core is not the most efficient).https://www.anandtech.com/show/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested/8 said:Some users might be scratching their heads – why is the second chiplet in both of these chips using less power, and therefore being more efficient? Wouldn’t it be better to use that chiplet as the first chiplet for lower power consumption at low loads? I suspect the answer here is nuanced – this first chipet likely has cores that enable a higher leakage profile, and then could arguably hit the higher frequencies at the expense of the power.